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ROBOTCORE UDP/IP

FPGA UDP/IP Networking Stack to push Robots to Nanosecond Speeds

ROBOTCORE® UDP/IP is an innovative FPGA robot core (also known as IP core), specifically engineered to significantly enhance the efficiency and speed of Internet Protocol (IP) networking stack communications utilizing the User Datagram Protocol (UDP). Designed with the cutting-edge demands of robotics and high-speed communication systems in mind, ROBOTCORE® UDP/IP can send or receive small packages in 700 nanoseconds, accelerating networking by more than 19x when compared to traditional CPUs. A pivotal component in modern real-time and fast networking robotic infrastructures.

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ROBOTCORE UDP/IP

Ultra-fast UDP/IP robot networking communications

ROBOTCORE® UDP/IP operates by accelerating the communication speed of the Internet Protocol (IP) networking stack through advanced FPGA hardware acceleration specifically tailored for UDP (User Datagram Protocol) communications. At its core, it implements a streamlined and optimized hardware IP and UDP stack processing mechanism, ensuring microsecond-level (us) rapid handling of network packets. This optimization results in significantly faster robot data transmission and reduced latency, crucial for real-time applications in robotics.

The architecture of ROBOTCORE® UDP/IP is designed to be highly scalable and flexible, enabling it to seamlessly integrate into a variety of FPGA and FPGA SoC technologies. It intelligently manages data throughput, ensuring high performance even while maintaining low power consumption. This makes it exceptionally effective in environments where energy efficiency is paramount. ROBOTCORE® UDP/IP can send small packages of 8-byte payloads in less than 1 us (700 ns) and 1024-byte packages in 3us, accelerating networking by more than 19x when compared to traditional CPUs. By accelerating the networking stack, ROBOTCORE® UDP/IP not only boosts data throughput but also maintains robust determinism and performance across diverse operational conditions, ensuring reliability in both industrial and research applications. Its working principle revolves around maximizing networking efficiency while minimizing resource usage, setting a new standard in robotic communication technology.

Benchmarks

Supported
hardware solutions

ROBOTCORE® UDP/IP supports the most popular FPGA silicon vendors and hardware acceleration solutions, including development kits to build robots with hardware acceleration and ROS.

ROBOTCORE® Robotic Processing Unit
Intel's Agilex 9
Intel's Agilex 7
Intel's Agilex 5
Intel's Agilex 3
AMD's Zynq 7000
AMD's Zynq Ultrascale+
AMD's Versal
Microchip's PolarFire
Intel's Agilex® 7 FPGA F-Series FPGA
AMD's KR260
AMD's ZCU102
Microchip's PolarFire Icicle Kit

Use
cases

ROBOTCORE® UDP/IP is particularly advantageous in scenarios where high-speed and reliable communication is paramount. It finds its ideal use in:

Industrial Automation
For fast and efficient communication between robotic components in manufacturing and assembly lines.

Teleoperation Systems
Facilitating smooth and responsive control of remotely operated robots.

Autonomous Vehicles
To ensure rapid data exchange for real-time decision-making in autonomous driving systems.

Research and Development
Providing a robust platform for developing and testing advanced robotic systems.

Faster ROS networking communications
with ROBOTCORE® UDP/IP

ROBOTCORE® UDP/IP significantly enhances the networking architecture of robotic systems, especially those utilizing ROS and ROS 2, by offering accelerated UDP/IP networking capabilities. Its integration into these popular robotic operating systems enables microsecond-level communication speeds, drastically improving real-time data processing and responsiveness. All while delivering the common ROS development flow when combined with ROBOTCORE® Framework.

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Deterministic
communications

Prior research[1],[2],[3],[4] helped uncover that traditional networking stacks in robotics have long struggled with indeterminism. ROBOTCORE® UDP/IP delivers absolute determinism via hardware. When compared to software-based solutions, it ensures that the communication latency is always the same, regardless of the load of the system. Crucial for real-time robotic systems.

  1. Gutiérrez, C. S. V., Juan, L. U. S., Ugarte, I. Z., & Mayoral-Vilches, V. (2018). Linux communications: an evaluation of the Linux communication stack for real-time robotic applications. arXiv preprint arXiv:1808.10821.
  2. Gutiérrez, C. S. V., Juan, L. U. S., Ugarte, I. Z., & Mayoral-Vilches, V. (2018). Towards a distributed and real-time framework for robots: Evaluation of ROS 2.0 communications for real-time robotic applications. arXiv preprint arXiv:1809.02595.
  3. Gutiérrez, C. S. V., Juan, L. U. S., Ugarte, I. Z., & Mayoral-Vilches, V. (2018). Time-sensitive networking for robotics. arXiv preprint arXiv:1804.07643.
  4. Gutiérrez, C. S. V., Juan, L. U. S., Ugarte, I. Z., Goenaga, I. M., Kirschgens, L. A., & Mayoral-Vilches, V. (2018). Time synchronization in modular collaborative robots. arXiv preprint arXiv:1809.07295.

Benchmarks

(plots are interactive)

LATENCY

(one-way)

Latency small packets (us)
(one-way maximum latency measured after 10K samples and while sending 8-byte payload packets with ROBOTCORE UDP/IP running in an FPGA@156MHz. Other fmax values may lead to better results.)

0.7 us

Latency 1024-byte payload (us)
(Same as above, but with 1024-byte payload packets)

2.95 us

ROUND-TRIP-TIME (RTT)

Round-Trip-Time Latency (us)
(Round-Trip-Time (RTT) average latency measured after 10K samples and while sending 8-byte payload packets with ROBOTCORE UDP/IP running in an FPGA@156MHz. CPU used for measurements corresponds with an Intel Core i5-13600K. A dashed line shows the maximum values observed for each case. )

RTT max. latency small packets (us)
(measured Round-Trip-Time (RTT) with 8-byte payload packets)

1.4 us

RTT max. latency 1024-byte payload (us)

5.9 us

SPEEDUP

Speedup when compared to traditional CPUs
(considering average latency measurements)

19x

Maximum speedup when compared to traditional CPUs
(considering maximum latency measurements)

86x

RESOURCES

% FPGA resource consumption (LUT, FF, DSP, BRAM)
(considering an AMD Zynq™ UltraScale+™ MPSoC EV (XCK26))

% FPGA resource consumption (LUT, FF, DSP, BRAM)
(considering an Intel Agilex® 7 FPGA F-Series, 1400 KLE, 2486A)

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